Packaging of the Ultra Large Scale Integration (ULSI) chip is one of the most important steps in ULSI manufacturing, contributing significantly to the overall cost, performance and reliability of the packaged chip. As semiconductor devices reach higher levels of integration, packaging technologies such as chip bonding have become increasingly important. Packaging of the chip accounts for a considerable portion of the cost of producing the device, and failure of the package leads to costly yield reduction.
As semiconductor device sizes have decreased, the density of devices on a chip has increased along with the size of the chip, thereby making chip bonding more challenging. One of the major problems leading to package failure as chip sizes increase is the increasingly difficult problem of thermal coefficient of expansion (TCE) mismatches between materials, leading to stress buildup and consequent failure. For example, in flip chip technology, chip bonding is accomplished by means of solder bumps formed on under bump metallization (UBM) layers overlying a chip bonding pad where, frequently, improper wetting (bonding) between the solder and UBM layers may lead to a bond not sufficiently strong to withstand such stresses.
In many cases, it is necessary to repackage the chip after a package failure, requiring costly detachment of the chip from the package and repeating the chip bonding process in a new package. Some chip bonding technologies utilize a solder bump attached to a contact pad (chip bonding pad) on the chip to make an electrical connection from the chip devices to the package. For example, C4 (Controlled-Collapse Chip Connection) is a means of connecting semiconductor chips to substrates in electronic packages. C4 is a flip-chip technology in which the interconnections are small solder balls (bumps) on the chip surface. Since the solder balls form an area array, C4 technology can achieve the highest density scheme known in the art for chip interconnections. The flip chip method has the advantage of achieving the highest density of interconnection to the device with the lowest parasitic inductance.
Solder bumps may be formed by, for example, vapor deposition of solder material over layers of under bump metallization (UBM) formed on the chip bonding pad. In another method, the layers of solder material may be deposited by electrodeposition onto a seed layer material deposited over UBM layers formed on the chip bonding pad. In yet another method, solder bumps may be formed by a solder-paste screen printing method using a mask (stencil) to guide the placement of the solder-paste. Typically, after deposition of the solder materials, for example, in layers or as a homogeneous mixture, the solder bump (ball) is formed after removing a photoresist mask defining the solder material location, by heating the solder material to a melting point where according to a reflow process, a solder ball is formed with the aid of surface tension. Alternatively, a solder bump (column) may be formed within a permanent mask made of photoresist or some other organic resinous material defining the solder bump area over the chip bonding pad.
In an exemplary process for forming a solder bump on a semiconductor chip, reference is made to FIGS. 1A–1E, representational of cross sections of an exemplary chip bonding pad and associated UBM layers and solder bump for chip bonding in flip chip technology. For example, with reference to FIG. 1A, the process of creating the solder bumps begins after chip bonding pad 10, for example Cu or Al, formed by vapor deposition, has been deposited on the surface of the semiconductor wafer 8. After the chip bonding pad 10 is formed, a passivation layer 12 of, for example, silicon dioxide (SiO2) is formed over the semiconductor device surface excluding a portion overlying the chip bonding pad 10. Typically, one or more under bump metallization (UBM) layers, e.g., 14A of from about 500 Angstroms to about 5000 Angstroms are then deposited over chip bonding pad 10 and a layer of photoresist 16 formed thereover, as shown in FIG. 1B. The UBM layer 14A may be, for example, a layer of titanium. The photoresist layer is typically from about 10 to about 25 microns high. As shown in FIG. 1B, the photoresist layer 16 is photolithographically patterned and developed to form an opening 17 above the contact pad 10 to expose the UBM layer, e.g., 14A. Additional UBM layers may be formed within the mask opening 17 by, for example, an electroplating process or vapor deposition process forming e.g., UBM layers 14B and 14C in FIG. 1C. Layers 14B and 14C may be, for example, layers of copper and nickel, respectively. UBM layers are formed over the chip bonding pad 10, for example, to allow for better bonding and wetting of the solder material to the uppermost UBM layer adjacent the solder material, e.g., 14C, and for protection of the chip bonding pad 10 by the lowermost UBM layer, e.g., 14A. A column of solder material 18A may either be deposited in layers, for example, a layer of Pb followed by a layer of Sn, the solder material layers later being formed into a homogeneous solder during reflow, or may be deposited as a homogeneous solder material by, e.g., vapor deposition or electroplating onto a seed layer (e.g., 14C).
After removal of the photoresist layer 16, the UBM layer 14A is etched through by a reactive ion etch (RIE) process to the underlying passivation layer 12 using the solder column 18A as an etching mask to protect the underlying UBM layers 14A, 14B, and 14C, as shown in FIG. ID. The solder column 18 is then heated to reflow to form a solder bump 18B over the UBM layer 14C, as shown in FIG. 1E. After reflow, a homogeneous Pb/Sn solder bump is formed including, for example, with composition ratios indicating weight percent, high lead alloys including 95 Pb/5 Sn (95/5) or 90 Pb/10 Sn (90/10) with melting temperatures in excess of 300° C. or eutectic 63 Pb/37 Sn (63/37) with a melting temperature of about 180° C. The solder bump forms a homogeneous material and has a well defined melting temperature. For example, the high melting Pb/Sn alloys are reliable bump metallurgies which are particularly resistant to material fatigue.
There is a need in the semiconductor processing art to develop improved solder bump compositions. As noted above, two major solder bump compositions are used in semiconductor assembly: (1) eutectic and (2) high lead. High lead solders have high performance characteristics, while eutectic solders have lower associated package costs. It is therefore an object of the invention to provide a method for solder bump formation using a combination of eutectic and high lead solders.